Semiconductor memory devices such as random access memory (RAM) devices typically include a number of memory cells coupled to at least one bit line. The memory cells often include at least one storage device, one storage node, and one access gate transistor. Generally, two storage transistors which are part of the storage device are coupled between two access gate transistors, and a bit line is coupled to each of the access gate transistors. Thus, each memory cell is often located between two bit lines.
The access gate transistors have gate electrodes which are coupled to word lines. A signal, such as, an address or a select signal, is provided on the word line associated with the memory cell to select or to access a particular memory cell. Once the memory cell is selected via the word line, the memory cell can be read or written to through the access gate transistors via the bit lines.
Semiconductor memory cells include static RAM devices (SRAMs). The memory cell of the SRAM often contains two inverters connected in anti-parallel. Basically, each cell is a flip-flop which has two stable states (e.g., a logic 1 or a logic 0). The memory cell is generally made of four or six transistors. In a four-transistor SRAM cell, a first resistor is coupled in series with a first pull down (e.g., storage or driver) transistor at a first storage node, and a second resistor is coupled in series with a second pull down transistor at a second storage node. A first access gate transistor is coupled between a first bit line and the first storage node, and a second access gate transistor is coupled between a second bit line and a second storage node.
In a six-transistor memory cell, the first and second resistors are replaced by first and second load transistors. The load transistors can be P-channel transistors, diodes, depletion mode N-channel transistors, or other load elements. The pull down transistors and the access gate transistors for both four-transistor cells and six-transistor cells are often N-channel enhancement mode transistors. The load transistors and the load resistors are coupled to a power node (e.g., VCC or VDD), and the driver transistors are coupled to a ground node (e.g., VSS). The power and the ground nodes as well as the bit lines are conventionally provided as metal conductive lines over the semiconductor substrate that are coupled to the memory cell by conductive vias. These metal conductive lines and vias increase the size of the integrated circuit which houses the memory cell.
To advance the storage capacity of memory devices, it has been desirable to house more memory cells on a semiconductor substrate. To house more memory cells, the space taken by the memory cell itself and its associated interconnections must be decreased. For example, in some prior art, six-transistor memory cells included six transistors formed laterally on the top surface of the substrate. This arrangement consumed valuable substrate area. Additionally, valuable space is also consumed by interconnections between the transistors, the bit lines, the power nodes, and the ground nodes.
Thus, there is a need for a memory cell of reduced size. Further, there is a need for a memory cell of minimal size which does not require extensive metal bit lines, power lines, and ground lines. Further still, there is a need for a compact memory cell optimized for internal interconnections.